`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/23 23:29:42
// Design Name: 
// Module Name: vga_ram_pic
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module vga_ram_pic(
       input clk,
       input rst,
       
       
       output hsync,
       output vsync,
       output [3:0]    vga_r,
       output [3:0]    vga_g,
       output [3:0]    vga_b

    );
    
    wire pclk;
    wire vga_clk_w;
    wire locked_w;
    wire rst_n_w;
    wire [11:0] pixel_data_w;
    wire [9:0] h_cnt;
    wire [9:0] v_cnt;  
    wire [11:0] vga_rgb;
    
    wire[31:0] data = 32'hffffffff;
    
    
   reg rst_n;
   always @(posedge clk)
   begin
        rst_n <= ~rst;
   end
    
    	  dcm_25m u0
         (
         // Clock in ports
          .clk_in1(clk),      // input clk_in1
          // Clock out ports
          .clk_out1(pclk),     // output clk_out1
          // Status and control signals
          .reset(rst_n));
          
         
          
          top_flyinglogo(
          .clk(clk),
          .pclk(pclk),
          .rst(rst), 
         // .data(data), 
         // .addr(), 
          .hsync(hsync), 
          .vsync(vsync), 
          .vga_r(vga_r), 
          .vga_g(vga_g), 
          .vga_b(vga_b));
          
endmodule
